International Journal of Application or Innovation in Engineering & Management
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ISSN 2319 – 4847
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Call for Paper, Published Articles, Indexing Infromation Design of Ternary Logic 8 bit Array Multiplier Based on Quantum Dot Gate FETs, Authors : Ravi Kishore A, Sandhya Rani M.H., International Journal of Application or Innovation in Engineering & Management (IJAIEM), www.ijaiem.org
Volume & Issue no: Volume 3, Issue 6, June 2014

Title:
Design of Ternary Logic 8 bit Array Multiplier Based on Quantum Dot Gate FETs
Author Name:
Ravi Kishore A, Sandhya Rani M.H.
Abstract:
Abstract In this paper, we discuss 8×8 array multiplier designs using the circuit model of three-state quantum dot gate field effect transistors(QDGFETs).QDGFETs produce one intermediate state between two normal stable ON and OFF states due to the change in the threshold voltage over this range. A simplified circuit model that accounts for this intermediate state was developed using this technique the design of 8bit array multiplier using the input three-state QDGFET gates is carried out. Increased number of states in the three-state QDGFETs will increase the number of bit handling capability of this device and will help us to handle more number of bits at a time with less circuit elements. Keywords: 8bitarray multiplier, Integrated circuit, quantum dot gate field effect transistor (QDGFET), Ternary logic, VLSI.
Cite this article:
Ravi Kishore A, Sandhya Rani M.H. , " Design of Ternary Logic 8 bit Array Multiplier Based on Quantum Dot Gate FETs " , International Journal of Application or Innovation in Engineering & Management (IJAIEM), Volume 3, Issue 6, June 2014 , pp. 289-299 , ISSN 2319 - 4847.
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