International Journal of Application or Innovation in Engineering & Management
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ISSN 2319 – 4847
www.ijaiem.org

Call for Paper, Published Articles, Indexing Infromation LOW POWER REGISTER DESIGN WITH INTEGRATION CLOCK GATING AND POWER GATING, Authors : D KoteswaraRao, T. Renushya Pale, International Journal of Application or Innovation in Engineering & Management (IJAIEM), www.ijaiem.org
Volume & Issue no: Volume 3, Issue 10, October 2014

Title:
LOW POWER REGISTER DESIGN WITH INTEGRATION CLOCK GATING AND POWER GATING
Author Name:
D KoteswaraRao, T. Renushya Pale
Abstract:
ABSTRACT In Integrated circuits a gargantuan portion of chip power is expended by clocking system which comprises of timing elements such as flip-flops, latches and clock distribution network. This paper enumerates power efficient design of shift registers using D flip-flops along with Clock and Power gating integration. Clock gating and power gating proves to be very effective solutions for reducing dynamic and active leakage power respectively. The two techniques are coupled in such a way that the clock gating information is used to drive the control signal of power-gating circuitry. In this paper, an activity driven fine-grained clock and power gating is proposed. First, a technique named Optimized Bus-Specific-Clock-Gating (OBSC) is introduced which reduces the problem of gated flip-flop selection by appropriate selection of subset of flip-flops. Then another technique named Run Time Power Gating (RTPG) is proposed for power gating the combinational logics performing redundant operations. The proposed shift registers are designed up to the layout level with 1V Power supply in 0.18um technology and simulated using Tanner Tools. Keywords: Optimized Bus-Specific-Clock-Gating (OBSC), Run Time Power Gating (RTPG).
Cite this article:
D KoteswaraRao, T. Renushya Pale , " LOW POWER REGISTER DESIGN WITH INTEGRATION CLOCK GATING AND POWER GATING " , International Journal of Application or Innovation in Engineering & Management (IJAIEM), Volume 3, Issue 10, October 2014 , pp. 117-122 , ISSN 2319 - 4847.
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