Review Paper on High Speed Parallel
Multiplierâ€“Accumulator (MAC) Based On
Radix-4 Modified Booth Algorithm

Gaurav Pohane, Sourabh Sharma

Abstract In this paper, A high speed and area-efficient merged multiply Accumulate (MAC) Units is proposed in this work. To realize the area-efficient and high speed MAC unit proposed in this work, first we examine the critical delays and hardware complexities of conventional MAC architectures to derive at a unit with low critical delay and low hardware complexity. The new architecture is based on combination of multiplication with accumulation and devising a hybrid type of carry save adder (CSA), for improved the performance. This can be implementing by using Radix-4 booth encoder. Power dissipation is acknowledged as a critical parameter in modern VLSI field. Reducing the overall area is achieved by the full utilization of the compressors instead of putting zeros in free inputs. Increasing the speed of operation is achieved by avoid using the modified compressor in the critical path. Feeding the bits of the accumulated operand into the summation tree before the final adder helps to increase the speed too. The proposed MAC unit and the previous merged. MAC unit are mapped on a Field Programmable Gate Array (FPGA) chip, in order to compare between them. The simulation result shows that the proposed system for 8-bit, 16-bit, and 32-bit MAC unit reduces area by 6.25%, 3.2 %, and 2.5% and increases the speed by 14%, 16%, and 19% respectively. Keywords:- Booth encoder, Radix-2 Booth Encoding multiplier, Radix-4 Booth Encoding multiplier, digital arithmetic, low power.

Title:	Review Paper on High Speed Parallel Multiplierâ€“Accumulator (MAC) Based On Radix-4 Modified Booth Algorithm
Author Name:	Gaurav Pohane, Sourabh Sharma
Abstract:	Abstract In this paper, A high speed and area-efficient merged multiply Accumulate (MAC) Units is proposed in this work. To realize the area-efficient and high speed MAC unit proposed in this work, first we examine the critical delays and hardware complexities of conventional MAC architectures to derive at a unit with low critical delay and low hardware complexity. The new architecture is based on combination of multiplication with accumulation and devising a hybrid type of carry save adder (CSA), for improved the performance. This can be implementing by using Radix-4 booth encoder. Power dissipation is acknowledged as a critical parameter in modern VLSI field. Reducing the overall area is achieved by the full utilization of the compressors instead of putting zeros in free inputs. Increasing the speed of operation is achieved by avoid using the modified compressor in the critical path. Feeding the bits of the accumulated operand into the summation tree before the final adder helps to increase the speed too. The proposed MAC unit and the previous merged. MAC unit are mapped on a Field Programmable Gate Array (FPGA) chip, in order to compare between them. The simulation result shows that the proposed system for 8-bit, 16-bit, and 32-bit MAC unit reduces area by 6.25%, 3.2 %, and 2.5% and increases the speed by 14%, 16%, and 19% respectively. Keywords:- Booth encoder, Radix-2 Booth Encoding multiplier, Radix-4 Booth Encoding multiplier, digital arithmetic, low power.
Cite this article:	Gaurav Pohane, Sourabh Sharma , " Review Paper on High Speed Parallel Multiplierâ€“Accumulator (MAC) Based On Radix-4 Modified Booth Algorithm " , International Journal of Application or Innovation in Engineering & Management (IJAIEM), Volume 3, Issue 11, November 2014 , pp. 086-095 , ISSN 2319 - 4847.
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