International Journal of Application or Innovation in Engineering & Management
An Inspiration for Recent Innovation & Research….
ISSN 2319 – 4847
www.ijaiem.org

Call for Paper, Published Articles, Indexing Infromation An Efficient Power Saving Latch Based Flip-Flop Design for Low Power Applications, Authors : N. KIRAN, K. AMARNATH, International Journal of Application or Innovation in Engineering & Management (IJAIEM), www.ijaiem.org
Volume & Issue no: Volume 4, Issue 12, December 2015

Title:
An Efficient Power Saving Latch Based Flip-Flop Design for Low Power Applications
Author Name:
N. KIRAN, K. AMARNATH
Abstract:
ABSTRACT In Integrated circuits a gargantuan portion of chip power is expended by clocking system which comprises of timing elements such as flip-flops, latches and clock distribution network. This paper enumerates power efficient design of shift registers using D flip-flops along with Clock and Power gating integration. In this paper we shown the Master-Slave design of D-Flip-Flop how we can reduce the number of transistors it the circuit. WE proposed a Latch based Flip-Flop which reduces the Master- Slave Network was shown. These circuits are designed and simulated using Tanner EDA Tools. Keywords: Clock Gating (CG), Power Gating (PG).
Cite this article:
N. KIRAN, K. AMARNATH , " An Efficient Power Saving Latch Based Flip-Flop Design for Low Power Applications " , International Journal of Application or Innovation in Engineering & Management (IJAIEM), Volume 4, Issue 12, December 2015 , pp. 074-081 , ISSN 2319 - 4847.
Full Text [PDF]                          Home