International Journal of Application or Innovation in Engineering & Management
An Inspiration for Recent Innovation & Research….
ISSN 2319 – 4847
www.ijaiem.org

Call for Paper, Published Articles, Indexing Infromation Low Power Consumption and Reduced Delay Borrow Save Adder Using Dynamic Design Logic, Authors : K.Dinesh kumar, Ramya jothikumar, International Journal of Application or Innovation in Engineering & Management (IJAIEM), www.ijaiem.org
Volume & Issue no: Volume 8, Issue 1, January 2019

Title:
Low Power Consumption and Reduced Delay Borrow Save Adder Using Dynamic Design Logic
Author Name:
K.Dinesh kumar, Ramya jothikumar
Abstract:
ABSTRACT An increase in delay fluctuation and reduction in operating frequency occurs due to low power consumption in Borrow Save Adder (BSA). Therefore, such circuits are not upto expected benefits. A new modulo ex-or adder based on carry correction technique and parallel prefix algorithm is proposed. The n-modulo adder can be divided into four units such as the preprocessing unit, the prefix computation unit, the carry correction unit, and the sum computation unit. In carry correction technique, the output carry from adder computed by prefix computation unit and the final carries is obtained by altering the information carries twice. Also prefix computations is done parallel and carry correction technique is carried out. The proposed modulo adder has better area delay performance and achieves faster operating frequency and it is implemented using Xilinx ISE 9.1/14.2. Keywords-Borrow Save Adder (BSA), Carry correction technique, Parallel prefix algorithm.
Cite this article:
K.Dinesh kumar, Ramya jothikumar , " Low Power Consumption and Reduced Delay Borrow Save Adder Using Dynamic Design Logic " , International Journal of Application or Innovation in Engineering & Management (IJAIEM), Volume 8, Issue 1, January 2019 , pp. 008-011 , ISSN 2319 - 4847.
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